Skip to content

Implement RV64 bit manipulation instructions on 32-bit registers #1157

Description

@pavelkryukov

RISC-V Bit Manipulation instructions often have ".*W" companion which operate on 32-bit registers in 64-bit mode. Your goal is to implement these instructions using existing code.

Activity

Sign up for free to join this conversation on GitHub. Already have an account? Sign in to comment

Metadata

Metadata

Assignees

No one assigned

    Labels

    3Features of medium complexity or infrastructure enhancementsS1 — ISATo solve the issue, you need knowledge about MIPS or RISC-V ISAenhancementAdds a new feature to simulation.good first issueGood task to start with MIPT-MIPS development

    Type

    No type

    Projects

    No projects

      Milestone

      No milestone

      Relationships

      None yet

      Development

      No branches or pull requests

      Issue actions