Verify correctness of read-after-write behavior

[pavelkryukov]

Some RISC-V instructions perform writes to 2 destinations, either 2 register or register or program counter. In cases if the source of one sub-operation matches a destination of another one, the order of result output is important. The examples are jalr and instruction operating with CSRs:

riscv-software-src/riscv-tests#258
riscv-software-src/riscv-tests#263

Your objective is to convert these test cases to unit tests, similarly to tests we have already:

mipt-mips/simulator/risc_v/t/unit_test.cpp

Lines 80 to 88 in 081acc6

	TEST_CASE("RISCV add")
	{
	CHECK( RISCVInstr<uint32>(0x00b505b3).get_disasm() == "add $a1, $a0, $a1");
	RISCVInstr<uint32> instr( "add", 0);
	instr.set_v_src( 0x10, 0);
	instr.set_v_src( 0xf, 1);
	instr.execute();
	CHECK( instr.get_v_dst() == 0x1f);
	}

After test implementation, you might have to fix our implementation of instructions in alu.h.
After that, you may build and run test binaries from trackers mentioned above.