Welcome to this repository for bare-metal firmware development on STM32 (Cortex-M) microcontrollers. This project focuses on writing low-level drivers from scratch by directly manipulating registers and utilizing hardware structures without relying on HAL.
The project is structured into progressive modules, moving from basic register manipulation to advanced interrupt-driven applications:
chip_headers/CMSIS: Core Cortex-M hardware abstraction and register definitions.0_led_toggle_addr&1_led_toggle_addr_struct: Introduction to memory-mapped I/O and register structures.
2_gpio_output&3_gpio_bsrr: Configuring pins as outputs using standard registers.4_gpio_input: Reading digital input signals.
5_uart_tx&8_uart_rx: Basic polling-based serial transmission and reception.6_uart_printf: Retargeting the standardprintf()function to output over UART for easier debugging.7_uart_modular: Clean, modular driver structure separating UART initialization and logic.16_uart_rx_interrupt: Non-blocking asynchronous data reception using interrupts.
9_adc_single_conversion: Sampling an analog signal once on demand.10_adc_continous_conversion: Continuous sampling modes for real-time signals.17_adc_interrupt: Handling ADC conversion completions asynchronously.
11_systick_delay&18_systick_interrupt: ARM Cortex-M internal system tick timer for precise delays.12_timers: Configuring hardware general-purpose timers.13_OutputCompare&14_InputCapture: Generating waveforms (PWM) and measuring external signal frequencies/pulse widths.19_timers_interrupt&tim2_interrupt: Working with periodic timer-overflow interrupts.
- Using the Nested Vectored Interrupt Controller (NVIC) to manage external and internal peripheral triggers.
docs/: Relevant technical documentation, reference manuals, and datasheets.logic analyzer outputs/: Saved waveforms and timing captures verifying that the protocols (UART, Timers, PWM) match physical hardware specifications exactly.
- Language: Embedded C
- Target Architecture: ARM Cortex-M4 (STM32)
- Development Flow: Direct register-level access (No HAL)