Single-Precision Floating-Point (FP32) Sigmoid Neuron Accelerator

Structural Verilog implementation of an IEEE 754 single-precision floating-point (FP32) datapath for Multi-Layer Perceptron (MLP) neural network inference. This repository decomposes a sigmoid neuron into modular floating-point arithmetic IP units, culminating in a 4-element streaming vector dot-product engine cascaded into an activation pipeline.

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Sub-Project Summary

Project 1: FP Multiplier-Subtractor (fp_ms)

• Objective: Integrate basic floating-point arithmetic IP components to process initial scaling and bias subtraction.
• Components: Instantiates FP_multiplier and FP_subber from FPU_Is_lib.v.
• Functionality: Multiplies an input dot-product scalar by IEEE 754 -1.0 (32'hbf800000) and passes the output to FP_subber to subtract the bias value bh_i.

Project 2: Sequence of MSSR (fp_mssr)

• Objective: Expand Project 1 into a full floating-point sequential transformation pipeline.
• Components: Cascades fp_ms, a second FP_subber module, and FP_reciprocal.
• Functionality: Subtracts a constant 1.0 (32'h3f800000) from the incoming pipeline signal, then computes the IEEE 754 floating-point reciprocal (1.0 / io_a).

Project 3: FP Vector Dot Product (fp_dot)

• Objective: Implement a 4-element streaming vector dot-product multiplier.
• Components: 4 parallel FP_multiplier units and a 2-stage binary adder tree using FP_adder modules.
• Functionality: Evaluates vector dot product for a streaming width of 4.

Project 4: Sigmoid Neuron Integration (sigmoid_neuron)

• Objective: Integrate Project 3 (fp_dot) and Project 2 (fp_mssr) into a standalone Sigmoid Neuron hardware module.
• Functionality: Connects the scalar IEEE 754 output of fp_dot into the input stage of fp_mssr along with bias parameter bh_i to output final signal yh_i.

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IEEE 754 Floating-Point Reference

FIGURE 5.2

IEEE 754 Standard (Single Precision): $(-1)^S \times (1.0 + M) \times 2^{(E-127)}$

• Sign: Bit 31
• Exponent: Bits 30:23
• Mantissa: Bits 22:0

TABLE 8.2: IEEE 754 Format for FP Numbers

FP	1.0	2.0	3.0	4.0	5.0	6.0
HW	3f800000	40000000	40400000	40800000	40a00000	40c00000
FP	7.0	8.0	9.0	10.0	11.0	12.0
HW	40e00000	41000000	41100000	41200000	41300000	41400000
FP	-1.0	-2.0	-3.0	-4.0	-5.0	-6.0
HW	bf800000	c0000000	c0400000	c0800000	c0a00000	c0c00000
FP	-7.0	-8.0	-9.0	-10.0	-11.0	-12.0
HW	c0e00000	c1000000	c1100000	c1200000	c1300000	c1400000

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Verification & Test Results

All primitives operate on active-low asynchronous resets (negedge reset). Testbenches verify hardware execution against the following dataset:

• Test Case 1:
  • Vector Inputs: w = [1.0, 2.0, 3.0, 1.0], x = [1.0, 2.0, 2.0, 1.0], bh_i = -2.0
  • fp_dot result: 12.0 (32'h41400000)
  • fp_ms result: 12.0 * (-1.0) - (-2.0) = -10.0 (32'hc1200000)
  • Final yh_i result: 1.0 / (-10.0 - 1.0) ≈ -0.0909

• Test Case 2:
  • Vector Inputs: w = [1.0, 2.0, 3.0, 1.0], x = [-1.0, -2.0, -1.0, -2.0], bh_i = 2.0
  • fp_dot result: -10.0 (32'hc1200000)
  • fp_ms result: -10.0 * (-1.0) - 2.0 = 8.0 (32'h41000000)
  • Final yh_i result: 1.0 / (8.0 - 1.0) ≈ 0.1428

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Submodule

The FPU library is provided by Xiaokun (Bobbie) Yang through the IC-Design repository: https://github.com/IC-Design-Lab/IC-Design

Project Files

• dut/: Design-under-test Verilog files
• tb/: Verilog testbench
• filelist/: ModelSim source file list
• sim/: ModelSim simulation script
• third_party/IC-Design/: FPU library included as a Git submodule

Setup

Clone the repository with its submodule:

git clone --recurse-submodules https://github.com/IC-Design-Lab/IC-Design

git submodule update --init --recursive

Simulation Open ModelSim in the sim directory and run:

do run

Acknowledgments

• Hardware architectural specifications and floating-point design concepts based on coursework material from Integrated Circuit Design: IC Design Flow and Project-Based Learning book by Dr. Xiaokun Yang (University of Houston-Clear Lake).