fix(spi): flush transmitter after write to prevent spurious reads (#1007)

[jdeblese]

Summary

Wait for SPI write transmissions to complete before re-enabling the receiver. If you don't, then code compiled for the samd21 with optimizations is fast enough to re-enable the receiver before the write occurs, resulting in occasional spurious bytes in the receive buffer. This does disable pipelined writes (partially counteracts 8243da6).

An alternative fix suggested in rust-embedded/embedded-hal#739 would be to have the flush occur at the start of a read instead of at the end of a write. That'd allow writes to be pipelined and mixed write/read transactions to work correctly, but requires more changes. I prefer to first fix the faulty behaviour with a minimal change.

Only fixes the sync implementation (regular and DMA), as I'm not familiar enough with the async to know if this is an issue there.

Checklist

• All new or modified code is well documented, especially public items
• No new warnings or clippy suggestions have been introduced - CI will deny clippy warnings by default! You may #[allow] certain lints where reasonable, but ideally justify those with a short comment.

[jbeaurivage]

Hmm. I'm willing to merge this as an immediate fix, but we should probably think about a better way to handle pipelining. The alternative solution does seem sound to me. I'll keep #1007 open for the time being to track a future pipelined implementation.