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Verilog import: strength-reduce divide-by-power-of-2 to a shift
enhancementNew feature or requestNew feature or requestStatus: Open.#252 In simtenHQ/simten;Verilog import: remaining yosys cell coverage
enhancementNew feature or requestNew feature or requestStatus: Open.#249 In simtenHQ/simten;- Status: Open.#195 In simtenHQ/simten;
- Status: Open.#193 In simtenHQ/simten;
- Status: Open.#192 In simtenHQ/simten;
- Status: Open.#191 In simtenHQ/simten;
- Status: Open.#190 In simtenHQ/simten;
- Status: Open.#189 In simtenHQ/simten;
@simten/mcp: make WebSocket bridge port configurable (currently hardcoded to 19847)
enhancementNew feature or requestNew feature or requestStatus: Open.#154 In simtenHQ/simten;- Status: Open.#147 In simtenHQ/simten;
- Status: Open.#146 In simtenHQ/simten;
- Status: Open.#145 In simtenHQ/simten;