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adpll
Here are 5 public repositories matching this topic...
All Digital Phase-Locked Loop (ADPLL)
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Sep 19, 2026 - Verilog
Two-tile all-digital PLL taped out on TinyTapeout SKY26c (SkyWater 130nm). Ring-oscillator DCO, counter-based TDC, PI loop filter. Locks 10 MHz reference to programmable output frequency up to 63x.
asic rtl verilog pll ring-oscillator physical-design tape-out adpll skywater openlane sky130 chip-design tinytapeout opensiliconhub digital-pll
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Sep 9, 2026 - Verilog
An All-Digital PLL (UMC 180nm) with a 25th-order FIR digital loop filter whose coefficients are trained by an ANN — achieving 2.26 GHz output, 8 ns lock time, and 5.3 mW power.
machine-learning neural-network vlsi verilog-hdl cadence-virtuoso fir-filter adpll digital-loop-filter
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Aug 20, 2026 - Jupyter Notebook
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