Build software better, together

Verilean / sparkle

A type-safe, formally verifiable HDL compiler in Lean 4. Inspired by Clash, built for high-assurance hardware synthesis.

hdl formal-verification risc-v hardware-synthesis lean4

Updated Sep 22, 2026
Lean

gussmith23 / lakeroad

Star

FPGA synthesis tool powered by program synthesis

fpga dsp program-synthesis hardware-synthesis technology-mapping

Updated Dec 15, 2025
Racket

tongplw / HW-Syn-Lab

Star

⚙Hardware Synthesis Laboratory Using Verilog

hardware verilog xilinx vivado uart vga basys3 hardware-synthesis

Updated May 10, 2020
Verilog

Zubax / holoso

Star

Verilog synthesis directly from idiomatic Python for numerical/DSP-heavy applications. Not an HDL.

fpga hls dsp verilog pipelining hdl high-level-synthesis softcore hardware-synthesis nisc zisc

Updated Sep 21, 2026
Python

srijavuppala / rtl_agent

Star

Agentic RTL generation pipeline: text/PDF/audio/video → Spec IR → Two-Oracle agent → verified SystemVerilog (GLSVLSI 2026)

eda multi-agent gemini rtl verilog verilog-hdl hardware-synthesis rtl-generation llm agentic-ai

Updated Jun 19, 2026
Jupyter Notebook

ArturWeber / navigating-the-memory-wall

Star

Design Space Exploration of bandwidth and latency constraints in SIMD neural accelerators using the Roofline model. Analyzes how memory bottlenecks impact EDP, GOPS, stall cycles, and hardware utilization through automated RTL synthesis with Python and industry-standard EDA tools.

simd rtl design-space-exploration systemverilog computer-architecture hardware-synthesis roofline-model edge-ai asic-design neural-accelerator energy-delay-product matrix-vector-unit

Updated Aug 26, 2026
Python

InvincibleJuggernaut / ALU

Star

Design for 4 bit ALU with essential logical and arithmetic modules.

verilog hardware-designs hardware-description-language hardware-synthesis arithmetic-logic-unit

Updated Oct 29, 2021
Verilog

natTP / 2110363-hw-syn-lab

Star

Code written during 2110363 HW SYN LAB I course, Academic Year 2021, Chulalongkorn University.

fpga verilog hardware-synthesis

Updated Feb 2, 2022
Verilog

EngineersBox / MCV

Star

Verilog to redstone compiler + synthesiser for Minecraft

minecraft redstone verilog hardware-synthesis

Updated Mar 5, 2023

kraftpunk97 / 8-bit-RISC-Microprocessor

Star

An 8-bit RISC Microprocessor made for my Embedded Systems course.

hardware verilog microprocessor risc xilinx-vivado hardware-synthesis

Updated Jul 11, 2024
Verilog

kazakma / ai_fpga

Star

Выпускная квалификационная работа: генератор аппаратных блоков функций активации для FPGA

fpga verilog fixed-point sat-solver smt-solver digital-design cyclone-iv hardware-synthesis intel-fpga activation-functions

Updated Jul 21, 2026
Verilog

omgbox / mbe-engine

Star

The Morphic Bitstream Engine (MBE) - A revolutionary computing architecture that processes raw binary data without traditional limitations

Updated Jul 24, 2026
Python

ovenror / librhdl

Star

a hardware synthesis library for Minecraft Redstone circuits

minecraft redstone hardware-synthesis

Updated May 20, 2026
C++

benallard / nextpnr-turingtumble

Star

A nextpnr arch definition for the TuringTumble board game.

fpga yosys hardware-synthesis turing-tumble nextpnr

Updated Nov 5, 2022
Verilog

JuhoArtturiHemminki / GTCSYN

Star

Non-dissipative computational engine implementing the Unitary Transduction Invariant (ΔI · Φ = W_rec). Bypasses the Landauer limit via Golden Ratio (Φ) phase-synchronization. Eliminates thermal resonance by re-channeling entropy into recirculative work. Written in Rust.