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pipelined
Here are 12 public repositories matching this topic...
Computer Architecture -VLSI -Verilog Codes-Xilinx-Irsim
pipeline verilog xilinx floating-point computer-architecture vlsi hardware-modules adder wallace-tree-multiplier iverilog floating-point-arithmetic pipelined carry-propogate-adders kogge-stone-adder sklansky-adder magic-tool gate-layout cmos-path-enumerator
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May 8, 2021 - Verilog
Synthesizable 16-bit, 16-stage pipelined CORDIC engine in Verilog (Q2.14 fixed-point) computing high-throughput sine and cosine without hardware multipliers. Features valid_in/valid_out handshaking and self-checking verification.
fpga rtl verilog finite-state-machine icarus-verilog hardware-acceleration verilog-hdl xilinx-vivado cordic digital-logic-design pipelined cordic-algorithm synthesizable fixed-point-arithmetic gtk-wave test-bench-verification synthesizable-verilog verilog-2001 digital-verification
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Mar 24, 2026 - Verilog
O(log k) Parallel FHE Conversion IP package featuring pipelined SystemVerilog RTL and Header-Only C++ Library. Designed to accelerate cryptographic pipelines by removing the sequential RNS bottleneck.
cryptography fpga core mrc rtl ip high-performance-computing systemverilog hardware-acceleration rns pipelined chinese-remainder-theorem asic-design parallel-prefixsum fully-homomorphic-encryption kogge-stone header-only-library fully-homomorphic-encryption-library
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May 26, 2026 - SystemVerilog
Oracle Advanced PL/SQL
oracle collections oracle-database oracle-sql pipelined oracle-19c demasy demasy-labs oracle-plsql demasylabs advanced-plsql
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Nov 15, 2022 - PLSQL
A 5-stage pipelined RV32IM core with caches and branch prediction, verified with RISC-V Formal and Spike lockstep co-simulation, booting FreeRTOS and running CoreMark on a Nexys Video FPGA.
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Sep 24, 2026 - SystemVerilog
Cached 5-stage Pipelined RV32I Processor (Team 19). Supports full RV32I base instructions and features a 2-way set-associative data cache. Highest verified milestone (Stretch Goals 1, 2, 3).
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Dec 12, 2025 - C++
The RTL implementation of a 8-bit pipelined signed integer multiplication module with some optimization techniques and testbench.
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Jul 14, 2026 - SystemVerilog
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