pipelined-processor

5-Stage Pipelined RISC-V CPU utilizing the RV32I ISA, featuring dynamic branch prediction. Designed, verified, performance tested, and ASIC-flowed

A 5-Stage Pipelined RISC-V Processor designed and implemented on FPGA (Artix-7 Nexys A7). Supports RV32I instructions set (R, I, S, B, U, J types) with ALU, control unit, hazard detection, forwarding, and pipeline registers. Verified through simulation and hardware testing with optimized timing and 4× performance gain.

A fully pipelined 5-stage RV32I processor implemented in SystemVerilog. This design models instruction-level parallelism with forwarding and hazard detection, and passes all RISCOF compliance tests for the RV32I base ISA.

RISC-V CPU Base Integer 32 bit ISA Implementation in Verilog HDL (Singlecycle, Multicycle, Pipelined). Update with more extension functionalities in the future.

A fault-tolerant, pipelined RISC-V processor system implemented in Verilog, featuring Triple Modular Redundancy (TMR), SECDED memory protection, error injection, and robust recovery mechanisms. Designed for research, education, and prototyping of reliable digital systems.

Synthesizable 5-stage pipelined RV32I processor in Verilog featuring full hazard handling (forwarding, load-use stalls, branch flushes) and an integrated 64-cycle 4×4 matrix multiplication coprocessor.

🧠 Pipelined Processor is to design, implement and test a Harvard (separate memories for data and instructions), RISC-like, five-stages pipeline processor.

A 5-stage pipelined 64-bit ARM processor; implemented in SystemVerilog

RISCape is a 5-stage pipelined RISC-V processor

Pipelined ARMv8 with hazard detection and forwarding - Computer Architecture course project - Computer Science @ FAMAF (UNC)

Four-stage pipelined RV32I/RV32F RISC-V SoC for the PYNQ-Z1, with a custom FPU, UART boot, and on-chip memories. Simulation to bitstream.

A 32 Bit RISC-V Processor Implementation in Verilog

SystemVerilog RTL implementation of a 5-stage pipelined RISC-V processor with hazard detection, forwarding, stall/flush control, simulation verification, and Vivado synthesis.

Processor designed to execute machine code instructions generated using an MIPS assembler. The assembler takes the machine code as input and performs the required operations.

A digital design project for a MIPS Reduced Instruction Set Computer (RISC) pipelined processor design that has a 5 stage basic pipeline and supports 32-bit MIPS instructions with an 8-bit wide datapath, on a 256x32 ROM and 256x8 RAM, implemented through structural VHDL

Synthesizable 5-stage pipelined RISC-V (RV32I) processor in Verilog. Verified in Vivado 2025.1 through post-implementation functional sim on XC7A200T. Timing met @ 83.33 MHz.

A 5-stage pipelined RV32I core in SystemVerilog. Full forwarding, load-use stalling, early branch resolution. RISCOF-verified against Spike, synthesized on a Zynq-7000.

5-stage pipelined RV32I processor in Verilog featuring hazard detection, forwarding, and RTL simulation-based verification.

Structural Verilog implementation of a pipelined RISC CPU datapath and control unit based on Mano & Kime.

Ongoing SystemVerilog RISC-V RV32I processor project targeting a five-stage pipeline, hazard handling, verification, and future ASIC implementation.