SecureRISC

A Hardware-Assisted Secure RISC-V-Style Processor

SecureRISC is a 32-bit RISC-V-style processor architecture implemented in Verilog RTL with hardware-assisted security mechanisms for instruction verification and memory protection.

The project explores how security policies can be enforced directly at the hardware level rather than relying only on software-based protection.

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Overview

Modern processors can encounter security threats involving malformed instructions and unauthorized memory accesses.

SecureRISC addresses these threats using two primary hardware security mechanisms:

• Enhanced Instruction Verification
• Memory Protection Unit (MPU)

These mechanisms are integrated into the processor datapath and verified through dedicated RTL testbenches, security attack simulations, and waveform analysis.

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Key Features

• 32-bit RISC-V-style processor architecture
• Arithmetic Logic Unit (ALU)
• Register file
• Program counter
• Instruction decoder
• Immediate generator
• Instruction memory
• Data memory
• Enhanced instruction verification
• Hardware Memory Protection Unit (MPU)
• Illegal instruction detection
• Instruction encoding validation
• Protected memory regions
• Unauthorized memory access detection
• Unauthorized memory access blocking
• CPU-level security attack simulation
• RTL simulation using Icarus Verilog
• Waveform analysis using GTKWave
• Automated GitHub Actions CI

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System Architecture

                         +----------------------+
                         |   Program Counter    |
                         +----------+-----------+
                                    |
                                    v
                         +----------------------+
                         |  Instruction Memory  |
                         +----------+-----------+
                                    |
                                    v
                         +----------------------+
                         | Instruction Verifier |
                         |    Security Check    |
                         +----------+-----------+
                                    |
                         Valid Instruction
                                    |
                                    v
                         +----------------------+
                         | Instruction Decoder  |
                         +----------+-----------+
                                    |
                    +---------------+---------------+
                    |                               |
                    v                               v
             +-------------+                +---------------+
             | Register    |                | Immediate     |
             | File        |                | Generator     |
             +------+------+                +-------+-------+
                    |                               |
                    +---------------+---------------+
                                    |
                                    v
                              +-----------+
                              |    ALU    |
                              +-----+-----+
                                    |
                                    v
                         +----------------------+
                         | Memory Protection    |
                         | Unit (MPU)           |
                         +----------+-----------+
                                    |
                         +----------+----------+
                         |                     |
                         v                     v
                  Authorized Access      Unauthorized Access
                         |                     |
                         v                     v
                  +-------------+       +----------------+
                  | Data Memory |       | Security       |
                  |             |       | Violation      |
                  +-------------+       +----------------+

FPGA Implementation Results

SecureRISC was successfully implemented using the open-source OSS CAD Suite FPGA toolchain. The design was synthesized and placed and routed for an ECP5 FPGA architecture.

Implementation Flow

Verilog RTL → Yosys Synthesis → Technology Mapping → Place & Route → Timing Analysis