Repository gathering basic modules for CDC purpose
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Dec 31, 2019 - SystemVerilog
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fgpa
Here are 47 public repositories matching this topic...
A collection of debugging busses developed and presented at zipcpu.com
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Jan 18, 2024 - Verilog
Audio Signal Processing SoC Project Website
audio university-project fpga-soc-linux de1-soc audio-signal-processing fpga-soc fgpa fpga-audio hardware-software-design
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Apr 6, 2017 - HTML
Graph Processing Framework that supports || OpenMP || CAPI
accelerator pagerank dfs benchmarking-suite ibm systemverilog bfs spmv capi betweenness-centrality triangle-counting graph-framework fgpa connected-components graph-algorithm altera-fpga sssp ibm-capi accelgraph-capi opencapi
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Aug 20, 2026 - SystemVerilog
This repository contains the source codes for design of circuits written in VHDL using Xilinx (14.7), which were practiced as a part of my CA lab during my BTech 4th semester.
college-assignment vhdl xilinx ise xilinx-ise fgpa vhdl-modules vhdl-code circuit-design vhdl-examples vhdl-testbench spartan3-fpga xilinx-ise-design-suite
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May 30, 2024 - VHDL
A secure RISC-V processor architecture for IoT devices featuring hardware-based memory protection, instruction verification, and modular RTL design using Verilog.
cpu processor riscv rtl verilog computer-architecture vlsi risc-v digital-design fgpa hardware-security
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Aug 23, 2026 - Verilog
Lightweight adventure game inspired by the classic Pokémon series, adapted to run on the DE2i-150 FPGA board.
pokemon real-time cpp hardware driver game-development raylib software drivers fgpa pokemon-game simple-project hardware-software quartus2 peripherals-identification de2i150-board
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Aug 14, 2025 - Verilog
Covers the DEEDS training material for electronic Design
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Jan 23, 2021 - VHDL
Implementation of 4-bit Arithmetic Logic Unit using structural modeling in Verilog. Features 8 operations controlled by 3-bit select line. Simulated on EDA Playground with waveform analysis.
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May 22, 2026 - Verilog
A C/C++ color-matching block shooter game developed using grid-based logic, VGA graphics, hardware key input, and recursive brick removal.
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Jul 14, 2026 - C++
Collection of RTL design projects implemented in VHDL and Verilog, including controllers, FSMs, and FPGA-ready modules.
fsm vhdl verilog vivado uart alu ghdl digital-design fgpa learning-portfolio rtl-design hardware-design
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Mar 1, 2026 - VHDL
Verilog HDL implementation of a Memory Management Unit (MMU) featuring virtual-to-physical address translation, page table lookup, memory protection, fault handling, and waveform-based verification.
verilog memory-management hardware-designs computer-architecture vlsi verilog-hdl digital-design fgpa memory-management-unit
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Jun 21, 2026 - Verilog
Minimal SoC design for alarm clock
c makefile assembly embedded-systems assembly-language alarm-clock systemverilog embedded-c fgpa assembly-x86
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Nov 12, 2020 - C
It contains 10 assignments based on simulation and testing of hardware codes on BASYS board.
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Jun 15, 2022 - VHDL
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