A small, light weight, RISC CPU soft core
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Sep 16, 2026 - Verilog
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wishbone
Here are 65 public repositories matching this topic...
Bus bridges and other odds and ends
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Sep 11, 2026 - Verilog
SD-Card controller, using either SPI, SDIO, or eMMC interfaces
spi-interface fpga verilog sd-card sdio wishbone verilog-components verilator axi emmc wishbone-bus sd-interface
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Aug 10, 2026 - Verilog
A simple, basic, formally verified UART controller
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Jan 29, 2024 - Verilog
A utility for Composing FPGA designs from Peripherals
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Aug 31, 2026 - C++
Simple UART controller for FPGA written in VHDL
fpga simulation controller vhdl uart ghdl wishbone uart-controller wishbone-bus cyc1000 uart-loopback
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Aug 7, 2021 - VHDL
A wishbone controlled scope for FPGA's
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Jan 12, 2024 - Verilog
A collection of debugging busses developed and presented at zipcpu.com
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Jan 18, 2024 - Verilog
同济大学CS《计算机系统实验》实验二TongJi University CS computer system experiment assignment 2《自己动手写 CPU》SOPC实现与操作系统移植
cpu gpio fpga uart sdcard big-endian wishbone ucosii sopc tongji-university ddr2 dynamic-pipelines openmips
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Jun 3, 2023 - Verilog
A wishbone controlled FM transmitter hack
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Jan 16, 2024 - Verilog
Implementation of a Serial Peripheral Interface(SPI) using Verilog and testing various modes of the SPI Device
spi-interface rtl verilog spi hdl testbench verilog-hdl wishbone spi-master spi-protocol spi-slave verilog-project clock-generator verilog-code verilog-rtl-model wishbone-master
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Jul 7, 2024 - Verilog
RISC-V Ibex core with Wishbone B4 interface
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May 30, 2026 - SystemVerilog
VexRiscV system with GDB-Server in Hardware
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Jul 5, 2023 - VHDL
A caravan equipped with API for creating bus protocols in Chisel with ease.
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Jan 15, 2026 - Scala
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